Shared transistor architecture with diagonally connected pixels for a CMOS image sensor

Yoshiharu Kudoh; Fumihiko Koga; Takashi Abe; Haruyuki Taniguchi; Maki Sato; Hiroaki Ishiwata; Susumu Ooki; Ryoji Suzuki; Hiroyuki Mori

doi:10.1117/12.704835

21 February 2007 Shared transistor architecture with diagonally connected pixels for CMOS image sensors

Yoshiharu Kudoh, Fumihiko Koga, Takashi Abe, Haruyuki Taniguchi, Maki Sato, Hiroaki Ishiwata, Susumu Ooki, Ryoji Suzuki, Hiroyuki Mori

Author Affiliations +

Proceedings Volume 6501, Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII; 65010G (2007) https://doi.org/10.1117/12.704835
Event: Electronic Imaging 2007, 2007, San Jose, CA, United States

Abstract

We have developed a pixel unit for CMOS image sensors (CISs) that has a shared transistor architecture with diagonally connected pixels. This pixel unit is composed of four photodiodes and seven transistors. It has a pixel size of 2.5-&mgr;m square. The transistors were designed using 0.18-micron aluminum process technology. Shared diffusion for reading signal electrons occurs between the corners of two photodiodes. The advantages of this layout include a long amplifier gate length and a large photodiode area.

Citation Download Citation

Yoshiharu Kudoh, Fumihiko Koga, Takashi Abe, Haruyuki Taniguchi, Maki Sato, Hiroaki Ishiwata, Susumu Ooki, Ryoji Suzuki, and Hiroyuki Mori "Shared transistor architecture with diagonally connected pixels for CMOS image sensors", Proc. SPIE 6501, Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII, 65010G (21 February 2007); https://doi.org/10.1117/12.704835

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