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21 February 2007 A CMOS vision chip for a contrast-enhanced image using a logarithmic APS and a switch-selective resistive network
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Abstract
In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a 160×120 pixel array was fabricated using a 0.35 &mgr;m double-poly four-metal CMOS technology, and its operation was experimentally investigated.
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Jae-Sung Kong, Sang-Heon Kim, Dong-Kyu Sung, Sang-Ho Seo, and Jang-Kyoo Shin "A CMOS vision chip for a contrast-enhanced image using a logarithmic APS and a switch-selective resistive network", Proc. SPIE 6501, Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII, 650110 (21 February 2007); https://doi.org/10.1117/12.703769
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