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26 February 2007 Dynamic power management for UML modeled applications on multiprocessor SoC
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Proceedings Volume 6507, Multimedia on Mobile Devices 2007; 65070Y (2007) https://doi.org/10.1117/12.707328
Event: Electronic Imaging 2007, 2007, San Jose, CA, United States
Abstract
The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed on a multiprocessor System-on-Chip (SoC) in a distributed manner. The UML models for both application and architecture are designed according to a well-defined UML profile for embedded system design, called TUT-Profile. Application processes are considered as elementary units of distributed execution, and their mapping on a multiprocessor SoC can be dynamically changed at run-time. Our approach on the dynamic power management balances utilized processor resources against current workload at runtime by (1) observing the processor and workload statistics, (2) re-evaluating the amount of required resources (i.e. the number of active processors), and (3) re-mapping the application processes to the minimum set of active processors. The inactive processors are set to a power-save state by using clock-gating. The approach integrates the well-known power management techniques tightly with the UML based design of embedded systems in a novel way. We evaluated the dynamic power management with a WLAN terminal implemented on a multiprocessor SoC on Altera Stratix II FPGA containing up to five Nios II processors and dedicated hardware accelerators. Measurements proved up to 21% savings in the power consumption of the whole FPGA board.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Petri Kukkala, Tero Arpinen, Mikko Setälä, Marko Hännikäinen, and Timo D. Hämäläinen "Dynamic power management for UML modeled applications on multiprocessor SoC", Proc. SPIE 6507, Multimedia on Mobile Devices 2007, 65070Y (26 February 2007); https://doi.org/10.1117/12.707328
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