5 April 2007 Enabling immersion lithography and double patterning
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Proceedings Volume 6518, Metrology, Inspection, and Process Control for Microlithography XXI; 65181M (2007); doi: 10.1117/12.714204
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States
Abstract
Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss some interim solutions for control of double patterning lithography (DPL), as well as some spacer-etch alternatives. We conclude with focus-exposure data showing some potential challenges for pitch-splitting strategies implemented in the context of immersion lithography.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin M. Monahan, Amir Widmann, "Enabling immersion lithography and double patterning", Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65181M (5 April 2007); doi: 10.1117/12.714204; https://doi.org/10.1117/12.714204
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KEYWORDS
Overlay metrology

Double patterning technology

Immersion lithography

Etching

Semiconducting wafers

Critical dimension metrology

Lithography

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