K1 factor for development and mass-production of memory devices has been decreased down to below 0.30 in
recent years. Process technology has responded with extreme resolution enhancement technologies (RET) and much
more complex OPC technologies than before. ArF immersion lithography is expected to remain the major patterning
technology through under 35 nm node, where the degree of process difficulties and the sensitivity to process
variations grow even higher. So, Design for manufacturing (DFM) is proposed to lower the degree of process
difficulties and advanced process control (APC) is required to reduce the process variations. However, both DFM
and APC need much feed-back from the wafer side such as hot spot inspection results and total CDU measurements
at the lot, wafer, field and die level.
In this work, we discuss a new design based metrology which can compare SEM image with CAD data and measure
the whole CD deviations from the original layouts in a full die. It can provide the full information of hot spots and
the whole CD distribution diagram of various transistors in peripheral regions as well as cell layout. So, it is possible
to analyze the root cause of the CD distribution of some specific transistors or cell layout, such as OPC error, mask
CDU, lens aberrations or etch process variation and so on. The applications of this new inspection tool will be
introduced and APC using the analysis result will be presented in detail.