Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond

Yiming Gu; James B. Friedmann; Vladimir Ukraintsev; Gary Zhang; Thomas Wolf; Tom Lii; Ricky Jackson

doi:10.1117/12.714479

5 April 2007 Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond

Yiming Gu, James B. Friedmann, Vladimir Ukraintsev, Gary Zhang, Thomas Wolf, Tom Lii, Ricky Jackson

Proceedings Volume 6518, Metrology, Inspection, and Process Control for Microlithography XXI; 651826 (2007) https://doi.org/10.1117/12.714479
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Resist trimming is a technique that is often used to close the gap between line widths which can be repeatedly printed with currently available lithography tools and the desired transistor gate length. For the 65-nm node, the resist line width delivered at pattern is between 60 to 70 nm while the final transistor gate length is usually targeted between 35 to 45 nm. The 15 to 35 nm critical dimension (CD) difference can be bridged by resist trimming. Due to the stringent gate CD budget, a resist trimming process should ideally have the following characteristics: i) no degradation in CD uniformity; ii) no damage in pattern fidelity; iii) controllable CD trim rate with good linearity; and iv) no degradation in line edge roughness (LER) or line width roughness (LWR). Unfortunately, a realistic resist trimming process is never perfect. In particular, resist consumption and the resultant internal stress build-up during resist trimming can lead to resist line bending. The effect of bent resist lines is a higher post-etch CD and significantly degraded local CD uniformity (LCDU). In order to reduce resist bending CD errors (defined as the difference between the post-etch CD and the design CD due to resist bending after trimming) several useful procedures either in layout or in processes are presented. These procedures include: i) symmetrically aligning gates to contact pads and field connecting poly in the circuit layout; ii) enlarging the distance between contact pad (or field connecting poly) to active area within the limits of the design rules (DR) and silicon real estate; iii) adding assist features to the layout within the DR limits; iv) minimizing resist thickness; and v) applying special plasma cure before resist trim.

Citation Download Citation

Yiming Gu, James B. Friedmann, Vladimir Ukraintsev, Gary Zhang, Thomas Wolf, Tom Lii, and Ricky Jackson "Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond", Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 651826 (5 April 2007); https://doi.org/10.1117/12.714479

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available