In-chip overlay metrology of 45nm and 55nm processes

Y. S. Ku; C. H. Tung; Y. P. Li; H. L. Pang; C. M. Ke; Y. H. Wang; D. C. Huang; N. P. Smith; L. Binns

doi:10.1117/12.713075

5 April 2007 In-chip overlay metrology of 45nm and 55nm processes

Y. S. Ku, C. H. Tung, Y. P. Li, H. L. Pang, C. M. Ke, Y. H. Wang, D. C. Huang, N. P. Smith, L. Binns

Proceedings Volume 6518, Metrology, Inspection, and Process Control for Microlithography XXI; 65182V (2007) https://doi.org/10.1117/12.713075
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

We have demonstrated the feasibility of measuring overlay using small targets with an optical imaging tool has in earlier papers. For 3&mgr;m or smaller targets, overlay shifts introduce asymmetry into the target image. The image asymmetry is proportional to the overlay shift and so this effect can be used to measure the overlay. We have used wafers built using production 45nm and 55nm processes to test these targets in production control situations. Targets with different programmed offsets allow the necessary conversion between image asymmetry and overlay shift to be determined empirically on the wafer under test. Measurements made using standard 25&mgr;m bar-in-bar targets and 3&mgr;m in-chip targets agree to within 10nm (3&sgr;). By processing results from five or more fields the agreement is improved to 5nm, a level which is limited by a mechanism other than random errors and which is similar to differences between different styles of bar-in-bar targets. Analysis of data from both in-chip and bar-in-bar targets shows similar patterns of overlay variation within the device area. The pattern of overlay variation does not fit mathematical models of overlay as a function of location. The total change of overlay within the field is 10nm, exceeds the overlay budget for critical layers at 45nm design rules. This uncontrolled in-field variation in overlay must be reduced and ideally eliminated if process control is to be achieved. A first step in controlling these errors is having an ability to measure them, and our data shows that this is possible with targets no larger than 3&mgr;m in total size.

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Y. S. Ku, C. H. Tung, Y. P. Li, H. L. Pang, C. M. Ke, Y. H. Wang, D. C. Huang, N. P. Smith, and L. Binns "In-chip overlay metrology of 45nm and 55nm processes", Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65182V (5 April 2007); https://doi.org/10.1117/12.713075

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KEYWORDS

Overlay metrology

Semiconducting wafers

Calibration

Data modeling

Mathematical modeling

Reticles

Wafer testing

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