The whole process of stochastic lithography simulation combined with an electron-beam
simulation module, could be useful in the validation of design rules taking into account fine details
such as line-edge roughness, and for simulating the layout before actual fabrication for design
inconsistencies. Material and process parameters can no more be considered of second order
importance in high-density designs. Line-width roughness quantification should accompany CD
measurements since it could be a large fraction of the total CD budget. An example of the effects of
exposure, material and processes on layouts are presented in this work using a combination of
electron beam simulation for the exposure part, stochastic simulations for the modeling of resist
film, the post-exposure bake, resist dissolution, and a simple analytic model for resist etching.
Particular examples of line-width roughness and critical dimension non-uniformity due to, material,
and process effects on the gate of a standard CMOS inverter layout are presented.