A multi-tiered approach to 193nm immersion defect reduction through track process adjustments

Eugenia Ng; Joshua Hooge

doi:10.1117/12.712361

23 March 2007 A multi-tiered approach to 193-nm immersion defect reduction through track process adjustments

Eugenia Ng, Joshua Hooge

Proceedings Volume 6519, Advances in Resist Materials and Processing Technology XXIV; 651926 (2007) https://doi.org/10.1117/12.712361
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

This paper discusses the optimization of process conditions on a 193 nm immersion lithography cluster tool to minimize defects. A 45 nm gate process was selected for optimization but a 65nm reticle was used for defect testing so that a nonimmersion baseline could be collected for comparison. Previous testing has shown defect counts and density are sensitive to rinsing of wafers before and after exposure. This sensitivity was dependent on the topcoat contact angle and resist-plus-topcoat porosity. This paper expands on that study in several ways. (1) The immersion process was simulated by scanning a develop rinse nozzle to observe, with a microscope, any peeling that could cause contamination in the exposure tool. (2) Different EBR strategies were compared to reduce defects causing by edge residue while maximizing the productive area of the wafer. (3) The appearance of some defect types was found to be related to the delay between exposure and post rinse. (4) Bake time and temperature were also added to the testing to determine if the impact to the film composition would influence the number of defects. (5) The addition of HMDS before BARC was tested as a way to control defects caused by delaminating at the edge of the wafer. The paper distinguishes between defects which are specific to the immersion process and those that would still be expected to occur in dry processing.

Citation Download Citation

Eugenia Ng and Joshua Hooge "A multi-tiered approach to 193-nm immersion defect reduction through track process adjustments", Proc. SPIE 6519, Advances in Resist Materials and Processing Technology XXIV, 651926 (23 March 2007); https://doi.org/10.1117/12.712361

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
10 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Head-mounted displays

Semiconducting wafers

Silicon

Thin film coatings

Photoresist processing

Scanners

Contamination

Show All Keywords

Keywords/Phrases

Search In:

Publication Years