23 March 2007 A multi-tiered approach to 193-nm immersion defect reduction through track process adjustments
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Abstract
This paper discusses the optimization of process conditions on a 193 nm immersion lithography cluster tool to minimize defects. A 45 nm gate process was selected for optimization but a 65nm reticle was used for defect testing so that a nonimmersion baseline could be collected for comparison. Previous testing has shown defect counts and density are sensitive to rinsing of wafers before and after exposure. This sensitivity was dependent on the topcoat contact angle and resist-plus-topcoat porosity. This paper expands on that study in several ways. (1) The immersion process was simulated by scanning a develop rinse nozzle to observe, with a microscope, any peeling that could cause contamination in the exposure tool. (2) Different EBR strategies were compared to reduce defects causing by edge residue while maximizing the productive area of the wafer. (3) The appearance of some defect types was found to be related to the delay between exposure and post rinse. (4) Bake time and temperature were also added to the testing to determine if the impact to the film composition would influence the number of defects. (5) The addition of HMDS before BARC was tested as a way to control defects caused by delaminating at the edge of the wafer. The paper distinguishes between defects which are specific to the immersion process and those that would still be expected to occur in dry processing.
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Eugenia Ng, Eugenia Ng, Joshua Hooge, Joshua Hooge, } "A multi-tiered approach to 193-nm immersion defect reduction through track process adjustments", Proc. SPIE 6519, Advances in Resist Materials and Processing Technology XXIV, 651926 (23 March 2007); doi: 10.1117/12.712361; https://doi.org/10.1117/12.712361
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