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23 March 2007 Formulated surface conditioners in 50 nm immersion lithography: simultaneously reducing pattern collapse and line-width roughness
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Abstract
With the introduction of immersion lithography into IC manufacturing for the 45nm node, pattern collapse and line width roughness (LWR) remain critical challenges that can be addressed by implementing formulated surface conditioners. Surface conditioners are capable of solving multiple issues simultaneously and are easily integrated into the post-develop photolithography process. In this paper, we assessed the impact and reported our findings using a formulated surface conditioning solution in an immersion lithography process to improve the non-pattern collapse and LWR process windows on 300mm Si wafers having 50 nm L/S features. The non-pattern collapse and LWR process window results were then compared to wafers processed using traditional developer processing methods, a DI Water (DIW) rinse. We report our findings using Focus Exposure Matrix (FEM) wafers having 50nm dense lines/spaces (L/S) and a 2.4:1 aspect ratio to determine the non-collapse and LWR process windows. An ASML TWINSCAN XT:1700TM Scanner and a 6%attPSM mask were used to pattern the FEM and LWR wafers. The wafers were then developed using an optimized developer recipe on an RF3iTM coater-developer track. Each wafer was analyzed and evaluated to determine the impact to CD and LWR with respect to the non-pattern collapse process window Formulated surface conditioners having dual capabilities, reduced pattern collapse and LWR, have demonstrated that multiple ITRS Roadmap goals can be achieved and easily implemented into standard IC processing in order to meet these challenges.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Minoru Sugiyama, Masakazu Sanada, Suping Wang, Patrick Wong, Stephan Sinkwitz, Manuel Jaramillo Jr., and Gene Parris "Formulated surface conditioners in 50 nm immersion lithography: simultaneously reducing pattern collapse and line-width roughness", Proc. SPIE 6519, Advances in Resist Materials and Processing Technology XXIV, 651927 (23 March 2007); https://doi.org/10.1117/12.712188
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