26 March 2007 Application of full-chip optical proximity correction for sub-60-nm memory device in polarized illumination
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Proceedings Volume 6520, Optical Microlithography XX; 65201R (2007); doi: 10.1117/12.711977
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States
As the design rule shrinks to its natural limit, reduction in lithography process margin and high Critical Dimension (CD) error gives rise to use of many Resolution Enhancement Techniques (RET). Recently, one the popular RET method to solve the above problem is polarized illumination. It is used to enhance the reduced lithography process margin and enhance CD uniformity. Polarization lithography basically uses one sided polarized light source. Therefore process margin increases for smaller design rule patterns. In this paper, we will present the results for polarized illumination based Optical proximity Correction (OPC) for sub-60nm memory device. First, models for polarization based and un-polarization based method will be compared for its model accuracy. Second, the process margin improvement for polarized and un-polarized illumination will be compared and analyzed for poly layer of sub-60nm memory device. Finally, method for further enhancing CD error within 5% for polarized OPC model will be discussed.
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Hyoung-Soon Yune, Yeong-Bae Ahn, Dong-jin Lee, James Moon, Byung-Ho Nam, Dong-gyu Yim, "Application of full-chip optical proximity correction for sub-60-nm memory device in polarized illumination", Proc. SPIE 6520, Optical Microlithography XX, 65201R (26 March 2007); doi: 10.1117/12.711977; https://doi.org/10.1117/12.711977

Optical proximity correction



Critical dimension metrology

Data modeling

Lithographic illumination

Resolution enhancement technologies

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