26 March 2007 A method for generating assist-features in full-chip scale and its application to contact layers of sub-70nm DRAM devices
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Abstract
ArF is still being used as a main light source for lithography of critical layers due to development delay of alternative light sources. The resolution enhancement is therefore mainly depends on increasing the NA of the projection lens or on decreasing the k1 value. Depth-of-focus is becoming narrower in both the approaches than ever. It has been well-known that properly designed assist-features can improve the process window of lithography, but optimizing assist-features is generally not a simple task, unless the pattern area is small or all the patterns are well isolated so that the proximity effect can be safely ignored. It is challenging to generate assist-features automatically when the pattern area is not small or the patterns are not well isolated, both of which is not a case in today's memory devices. Today's memory chip has such a large pattern area that it easily occupies a large portion of the available imaging field of today's scanner. The proximity effect cannot be safely ignored because k1 factor is low in today's memory devices and the patterns are not isolated even in peripherals. A new method to generate assist-features has been internally developed. This method is based on optical simulation and utilizes the optical characteristic of the exposure tool to maximize the process margin, and is scalable to the full-chip scale. Side-lobes are automatically suppressed well under the imaging threshold. The total processing time is comparable to a usual model OPC processing time. The present paper demonstrates a test case of this new method to a contact layer of full-chip sub-70nm DRAM device and the improvement of depth-of-focus. The increased depth-of-focus was equivalent to 18% reduction of contact CD at the same depth-of-focus.
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Dong-Woon Park, Sangwook Kim, Chan Hwang, Sukjoo Lee, Han-Ku Cho, Joo-Tae Moon, "A method for generating assist-features in full-chip scale and its application to contact layers of sub-70nm DRAM devices", Proc. SPIE 6520, Optical Microlithography XX, 652028 (26 March 2007); doi: 10.1117/12.713055; https://doi.org/10.1117/12.713055
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