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26 March 2007 The calibration of process window model for 55-nm node
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Abstract
In previous OPC model calibrations, most of the work was focused on how to calibrate a model for the best process conditions. With process tolerance decreasing in coming lithography generations, it is increasingly important to be able to predict pattern behavior through process window. Due to a low k1 factor that leads to a smaller process window, the use of process window models is required for both optical proximity correction (OPC) and Lithography Rule Check (LRC) applications to insure silicon success. In this paper, we would try to calibrate multiple process window models. The resulting models will be verified and judged using additional measurement data to demonstrate the quality.
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Te Hung Wu, Sheng Yuan Huang, Chia Wei Huang, Pei Ru Tsai, Chuen Huei Yang, Irene Yi-Ju Su, and Brad Falch "The calibration of process window model for 55-nm node", Proc. SPIE 6520, Optical Microlithography XX, 65203A (26 March 2007); https://doi.org/10.1117/12.715496
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