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Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs
Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations
Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability
Improving the power-performance of multicore processors through optimization of lithography and thermal processing
The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths
DFM flow by using combination between design based metrology system and model based verification at sub-50nm memory device