The feasibility of Hot Spot Fixing (HSF) system in DfM flow is studied and reported. Hot spot fixing using process
simulation is indispensable under low-k1 lithography process for logic devices with advanced design rule (DR). Hot
spot such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Proper
calibration of DR, mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect
correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with most
careful calibration of every process, unexpected potential hot spots are occasionally left in the design layout 1-2. OPC
optimization is useful for maximizing common process margin, but it cannot expand individual pattern's process margin
without modification of design layout.
So, at an early design stage, hot spot extraction using lithography compliance check (LCC) and manual modification of
design at hot spots will be a simple and useful method. The problem is that, it is difficult to determine how to modify
layout in order to be consistent with DR, MDP/OPC rule. For proper layout modification, intimate knowledge of the
entire process would be necessary, and moreover, the modification work often tends to be iterative, and thus time-consuming.
Therefore, using our automated HSF system in the cell design stage and also the chip design stage is helpful
for fixing design layout while avoiding fatal hot spot occurrence, with enough process margin and also with short
turnaround time (TAT) 3-4.
The basic system flow in the developed system is as follows;
LCC extracts potential hot spots, and the hot spots are categorized by lithography error mode, grade, and surrounding
context. And then, hot spot modification instructor, taking the surrounding situation into consideration, generates
modification guide for every hot spot. Design data is automatically modified according to the instruction at every hot
spot, complying with the design rule. The design modification process is verified with design-rule checker (DRC) and
process simulation to confirm hot spot elimination without side effect.
In this work, HSF is implemented in the design flow for various logic devices of 65 nm node. We extend modification
target layers to multiple critical layers, including active area, poly, local metal wire and intermediate metal wire. The
feasibility of the provided HSF system has been studied by applying it to around one hundred data of various sizes with
respect to pattern fixing rate and turn around time (TAT). Moreover, process margin expansion including depth of focus
(DOF) and exposure latitude (EL), in small layout was verified using process simulation and also by experimental
results, namely, scanning electron microscope (SEM) images of focus exposure matrix. The detailed results are shown
in the paper.