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21 March 2007 Patterning effect and correlated electrical model of post-OPC MOSFET devices
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Accurate simulation of today's devices needs to account for real device geometry complexities after the lithography and etching processes, especially when the channel length shrinks to 65-nm and below. The device performance is believed to be quite different from what designers expect in the conventional IC design flow. The traditional design lacks consideration of the photolithography effects and pattern geometrical operations from the manufacturing side. In to order obtain more accurate prediction on circuits, an efficient approach to estimate nonrectangular MOSFET devices is proposed. In addition, an electrical hotspot criterion is also proposed to investigate and verify the manufacturability of devices during patterning processes. This electrical rule criterion will be performed after the regular Design Rule Check (DRC) or Design for Manufacturing (DFM) rule check. Photolithography and industrial-strength SPICE model are taken into consideration to further correlate the process variation. As a result, the correlation between process-windows and driving current variation of devices will be discussed explicitly in this paper.
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Y. C. Cheng, T. H. Ou, M. H. Wu, W. L. Wang, J. H. Feng, W. C. Huang, C. M. Lai, R. G. Liu, and Y. C. Ku "Patterning effect and correlated electrical model of post-OPC MOSFET devices", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210G (21 March 2007);

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