Paper
21 March 2007 Improving the power-performance of multicore processors through optimization of lithography and thermal processing
A. H. Gabor, T. Brunner, S. Bukofsky, S. Butt, F. Clougherty, S. Deshpande, T. Faure, O. Gluschenkov, K. Greene, J. Johnson, N. Le, P. Lindo, A. P. Mahorowala, H-J. Nam, D. Onsongo, D. Poindexter, J. Rankin, N. Rohrer, S. Stiffler, A. Thomas, H. Utomo
Author Affiliations +
Abstract
It is generally assumed that achieving a narrow distribution of physical gate length (Lpoly) for the poly conductor layer helps improve power performance metrics of modern integrated circuits. However, in advanced 90 nm technologies, there are other drivers of chip performance. In this paper we show that a global optimization of all variables is necessary to achieve the optimum performance at the lowest leakage. We will also describe how systematic physical gate-length variation can improve core matching in multicore designs.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A. H. Gabor, T. Brunner, S. Bukofsky, S. Butt, F. Clougherty, S. Deshpande, T. Faure, O. Gluschenkov, K. Greene, J. Johnson, N. Le, P. Lindo, A. P. Mahorowala, H-J. Nam, D. Onsongo, D. Poindexter, J. Rankin, N. Rohrer, S. Stiffler, A. Thomas, and H. Utomo "Improving the power-performance of multicore processors through optimization of lithography and thermal processing", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210K (21 March 2007); https://doi.org/10.1117/12.711750
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Cited by 6 scholarly publications.
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KEYWORDS
Critical dimension metrology

Diffusion

Etching

Lithography

Semiconducting wafers

Cadmium

Integrated circuits

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