Hardware verification of litho-friendly design (LfD) methodologies

Reinhard März; Kai Peter; Sonja Gröndahl; Klaus Keiner; Byoung Il Choi; Shyue Fong Quek; Mei Chun Yeo; Nan Shu Chen; Soo Muay Goh

doi:10.1117/12.713995

21 March 2007 Hardware verification of litho-friendly design (LfD) methodologies

Reinhard März, Kai Peter, Sonja Gröndahl, Klaus Keiner, Byoung Il Choi, Shyue Fong Quek, Mei Chun Yeo, Nan Shu Chen, Soo Muay Goh

Author Affiliations +

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65210M (2007) https://doi.org/10.1117/12.713995
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

With the upcoming technology generations, it will become more and more challenging to provide a good yield and a fast yield ramp. The contribution of Resolution Enhancement Technologies (RET) to Design for Manufacturability (DfM) targets is to provide a good printability over the whole process window and the control by print image simulation (PW-ORC) and to identify and remove yield issues imprinted in the drawn layout in early phases of the design flow. Such a lithography-aware design data flow, which we call LfD (Litho-friendly Design) will be a very important step towards a fully developed DfM environment. We report in this paper the application of a LfD design flow used for library cells at the MAPLE, an Infineon 65 nm design prototype fabricated by Chartered. The results of the process variability analysis are verified by experimental results (dose-focus exposure matrices).

Citation Download Citation

Reinhard März, Kai Peter, Sonja Gröndahl, Klaus Keiner, Byoung Il Choi, Shyue Fong Quek, Mei Chun Yeo, Nan Shu Chen, and Soo Muay Goh "Hardware verification of litho-friendly design (LfD) methodologies", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210M (21 March 2007); https://doi.org/10.1117/12.713995

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