21 March 2007 Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node
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In this paper the impact of overlay and CD uniformity specifications on device and SRAM cell functional and parametric yield are analyzed. The variation of channel strain due to partial etching of the stress layer is determined, and we find that including this effect in the device parametric yield leads to severe CDU and overlay requirements. The method is applied to SRAM cells and memories, and it is shown that only the co-optimization of SRAM cell layout, CDU and overlay can increase the number of good dies per wafer.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Axel Nackaerts, Axel Nackaerts, Staf Verhaegen, Staf Verhaegen, Mircea Dusa, Mircea Dusa, Hans Kattouw, Hans Kattouw, Frank van Bilsen, Frank van Bilsen, Serge Biesemans, Serge Biesemans, Geert Vandenberghe, Geert Vandenberghe, } "Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210N (21 March 2007); doi: 10.1117/12.713385; https://doi.org/10.1117/12.713385

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