As the minimum transistor length is getting smaller, the variation and uniformity of transistor length seriously effect
device performance. So, the importance of optical proximity effects correction (OPC) and resolution enhancement
technology (RET) cannot be overemphasized. However, OPC process is regarded by some as a necessary evil in device
performance. In fact, every group which includes process and design, are interested in whole chip CD variation trend and
CD uniformity, which represent real wafer.
Recently, design based metrology systems are capable of detecting difference between data base to wafer SEM image.
Design based metrology systems are able to extract information of whole chip CD variation. According to the results,
OPC abnormality was identified and design feedback items are also disclosed. The other approaches are accomplished on
EDA companies, like model based OPC verifications. Model based verification will be done for full chip area by using
well-calibrated model. The object of model based verification is the prediction of potential weak point on wafer and fast
feed back to OPC and design before reticle fabrication. In order to achieve robust design and sufficient device margin,
appropriate combination between design based metrology system and model based verification tools is very important.
Therefore, we evaluated design based metrology system and matched model based verification system for optimum
combination between two systems. In our study, huge amount of data from wafer results are classified and analyzed by
statistical method and classified by OPC feedback and design feedback items. Additionally, novel DFM flow would be
proposed by using combination of design based metrology and model based verification tools.