Impacts of optical proximity correction settings on electrical performances

Meng-Fu You; Philip C. W. Ng; Yi-Sheng Su; Kuen-Yu Tsai; Yi-Chang Lu

doi:10.1117/12.711850

21 March 2007 Impacts of optical proximity correction settings on electrical performances

Meng-Fu You, Philip C. W. Ng, Yi-Sheng Su, Kuen-Yu Tsai, Yi-Chang Lu

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65210W (2007) https://doi.org/10.1117/12.711850
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength regime. The poly gate distortion affects device electrical characteristics, including drive current (I_on), leakage current (I_off), and threshold voltage (V_t). For circuits sensitive to layout, such as compact memory cells, electrical performances can vary with image distortion of each transistor even after applying resolution enhancement technologies (RETs) such as optical proximity corrections. In this paper, we demonstrate the impact of OPC settings on the performance of 6T-SRAM cells. The printed transistor gate and active region patterns are simulated by an in-house OPC engine. The device model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of smaller rectangles. Consequently, Electrical performance such as static noise margin (SNM) can be obtained by incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as segmentation length and numbers of corrections can affect wafer image quality and electrical performance in different ways.

Citation Download Citation

Meng-Fu You, Philip C. W. Ng, Yi-Sheng Su, Kuen-Yu Tsai, and Yi-Chang Lu "Impacts of optical proximity correction settings on electrical performances", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210W (21 March 2007); https://doi.org/10.1117/12.711850

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