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21 March 2007 Lithography enhanced manufacturability analysis by using multilevel simulated contours
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Abstract
Since the sub-50nm logic lithography approaches to k1 value of 0.3, it seems to be an impossible task to print typical logic patterns composed of random shapes and mixed pitches using the conventional resolution enhancement technology (RET). As one of the effective solutions to deal well with this issue, lithography friendly design (LFD) and advanced optical proximity correction (OPC) technology have been considered and developed. However, the investigation on the distortion types of various 2-dimensional patterns has rarely been preceded up to now, while lithographical hot spots are observed are dominated by the 2-dimensional patterns rather than in the 1-dimensional patterns. In order to provide a LFD layout and a good OPC performance for the future node logic device, the analysis and the hot spot's classification of the 2-dimensional pattern need to be performed. Based on our analysis of various pattern types at mimic-logic test block, a feedback strategy was implemented to reduce the 2-dimensional hot spots through the correction stage of the OPC recipes. In our study, we find out the proper value of ground rule and the cost-effective methodology which should go with reciprocal encouragement in OPC and LFD. This will give us a good methodology for the lithography technology nodes and upstream design for manufacturability (DFM) approaches.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Beom-Seok Seo, Woon-Hyuk Choi, Jong-Woon Park, Soung-Su Woo, and Sung-Ho Lee "Lithography enhanced manufacturability analysis by using multilevel simulated contours", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210Y (21 March 2007); https://doi.org/10.1117/12.711825
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