Wire sizing and spacing for lithographic printability optimization

Ke Cao; Jiang Hu; Mosong Cheng

doi:10.1117/12.708974

21 March 2007 Wire sizing and spacing for lithographic printability optimization

Ke Cao, Jiang Hu, Mosong Cheng

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 652111 (2007) https://doi.org/10.1117/12.708974
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

As the VLSI feature size has already decreased below lithographic wavelength, the printability problem due to strong diffraction effects poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development of Resolution Enhancement Techniques (RET) can alleviate the printability problem but cannot reverse the trend of deterioration. Moreover, over-usage of RET may dramatically increase photo-mask cost and increase the cycle time for volume production. Thus, there is a strong demand to consider the sub-wavelength printability problem in circuit layout designs. However, layout printability optimization should not degrade circuit timing performance. In this paper, we introduce a wire sizing and spacing method to improve wire printability with minimal adverse impact on interconnect timing performance. A new printability model is proposed to handle partially coherent illuminations. The difficult problem of printability optimization due to its multimodal nature is handled with a sensitivity based heuristic in timing aware fashion. Lithographic simulation results show that our approach can improve the printability in term of EPE (Edge Placement Error) by 20%-40% without violating timing, wire width and spacing constraints.

Citation Download Citation

Ke Cao, Jiang Hu, and Mosong Cheng "Wire sizing and spacing for lithographic printability optimization", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652111 (21 March 2007); https://doi.org/10.1117/12.708974

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KEYWORDS

Lithography

Resolution enhancement technologies

Photomasks

Optical proximity correction

Image segmentation

Semiconducting wafers

Silicon

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