Double patterning technology: process-window analysis in a many-dimensional space

Apo Sezginer; Bayram Yenikaya

doi:10.1117/12.711515

21 March 2007 Double patterning technology: process-window analysis in a many-dimensional space

Apo Sezginer, Bayram Yenikaya

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 652113 (2007) https://doi.org/10.1117/12.711515
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive images of ¹/₄-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces. We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling the space-width to ±10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows that overlay and etch bias are the most significant contributors to the variability of spaces. 3&sgr;[space-width] = 17% and 11% of nominal space can be achieved for 3&sgr;[Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array printed using NA=0.93.

Citation Download Citation

Apo Sezginer and Bayram Yenikaya "Double patterning technology: process-window analysis in a many-dimensional space", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652113 (21 March 2007); https://doi.org/10.1117/12.711515

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