Paper
21 March 2007 Novel technique to separate systematic and random defects during 65nm and 45nm process development
Author Affiliations +
Abstract
Defect inspections performed in R&D may often result in 100k to 1M defect counts on a single wafer. Such defect data combine systematic and random defects that may be yield limiting or just nuisance defects. It is difficult to identify systematic defects from defect wafer map by traditional defect classification where random sample of 50 to 100 defects are reviewed on review SEM. Missing important systematic defect types by traditional sampling technique can be very costly in device introduction. Being able to efficiently sample defects for SEM review is not only challenging, but can result in a Pareto that lacks in usefulness for R& D and for yield improvement. To mitigate the issue and to reduce yield improvement cycle in advanced technology, a novel method has been proposed. Instead of using random sampling method, we have applied a pattern search engine to correlate defect of interest (DOI) to its pattern background. Based on the approach we have identified an important defect type, STI cave defect, to be the major defect type on defect Pareto. For the defect type, stack die map was generated that indicated a distinctive signature. The result was compared against design layout to confirm that the defects were occurring at certain locations of design layout. Afterwards the defect types were reviewed using SEM and in-line FIB for further confirmation. We have found the cause of this void defect type to be poor gap-fill in deposition step. Based on the novel technique, we were able to filter out a systematic defect type quickly and efficiently from wafer map that consist of random and systematic defects.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
J. H. Yeh and Allen Park "Novel technique to separate systematic and random defects during 65nm and 45nm process development", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652114 (21 March 2007); https://doi.org/10.1117/12.711512
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Cited by 12 scholarly publications.
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KEYWORDS
Scanning electron microscopy

Semiconducting wafers

Defect inspection

Inspection

Defect detection

Yield improvement

Classification systems

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