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21 March 2007 Scanner parameter sensitivity analysis for OPE
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Abstract
The imaging power of microlithographic lenses, normalized to minimum feature size, has become lower and lower for each generation, even with the progress of high-NA lithography. The rate of increase of NA has not kept pace with Moore's law. Therefore, low k1 lithography techniques such as RET (Resolution Enhancement Technology) have been applied for more than a decade. RET, however, is a technique to increase the imaging contrast only for dedicated pattern types/sizes, and may decrease the imaging power for other than dedicated patterns. To fill this gap between actual imaging power and required imaging power, OPC (Optical Proximity Correction) technologies are becoming more and more important for leading edge lithography. The accuracy of OPC is important for high performance quality chips. On the other hand, due to low relative imaging power and high NA of the current projection lens, imaging performance is very sensitive to various kinds of errors such as defocus, dose error, aberration, apodization, flare, polarization aberration, polarization status, etc. In order to solve this, scanner parameters, which can be obtained even before the scanner itself has been completed, should be embedded in the imaging simulation in OPC design and verification to improve the accuracy. In addition, OPE (Optical Proximity Effect) data simulated with the scanner parameters may be useful for early stage reticle design before actual exposure using first lot scanners. We have studied the sensitivity of OPE to scanner parameters and prioritized parameters to be input to the OPC design and/or verification process for improving the accuracy without significant increase in the amount of calculation.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tomoyuki Matsuyama, Toshiharu Nakashima, Tomoharu Fujiwara, and Yuki Ishii "Scanner parameter sensitivity analysis for OPE", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652116 (21 March 2007); https://doi.org/10.1117/12.711356
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