Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Travis Brist; Le Hong; Ayman Yehia; Tamer Tawfik; Shumay Shang; Kyohei Sakajiri; John L. Sturtevant

doi:10.1117/12.712748

21 March 2007 Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Travis Brist, Le Hong, Ayman Yehia, Tamer Tawfik, Shumay Shang, Kyohei Sakajiri, John L. Sturtevant

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65211L (2007) https://doi.org/10.1117/12.712748
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC manufacturer data preparation flows as k₁ is pushed lower with each technology node. The use of this technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB options are explored for the gate layer by using new characterization and optimization functions available in the latest generation of correction and OPC verification tools. These include the ability to quantify across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus, exposure, and misalignment, and it is shown that significant improvements to CD control through the full manufacturing variability window can be realized.

Citation Download Citation

Travis Brist, Le Hong, Ayman Yehia, Tamer Tawfik, Shumay Shang, Kyohei Sakajiri, and John L. Sturtevant "Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211L (21 March 2007); https://doi.org/10.1117/12.712748

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