Real-time VT5 model coverage calculations during OPC simulations

Ioana Graur; Scott Mansfield; Moahmed Gheith; Mohamed Al-Imam

doi:10.1117/12.712394

21 March 2007 Real-time VT5 model coverage calculations during OPC simulations

Ioana Graur, Scott Mansfield, Moahmed Gheith, Mohamed Al-Imam

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65211R (2007) https://doi.org/10.1117/12.712394
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

For a robust OPC solution, it is important to isolate and characterize the detractors from high quality printability. Failure in correctly rendering the design intent in silicon can have multiple causes. Model inability in predicting lithographic and process implications is one of them. Process model accuracy is highly dependant on the quality of data used in the calibration phase of the model. Structures encountered during the OPC simulation that have not been included in the calibration patterns, or even structures somewhat similar to those used in calibration, are some times incorrectly predicted. In this paper a new method for studying VT5 model coverage during OPC simulations is investigated. The aerial image parameters for a large number of test structures used for model calibration are first calculated. A novel sorting and data indexing algorithm is then applied to classify the computed data into fast accessible look-up tables. These tables are loaded in the beginning of a new OPC simulation where they are used as a reference for comparing aerial image parameters calculated for new design fragments. Such new approach enables real time classification of design fragments based on how well covered they are by the VT5 model. Employing this method avoids catastrophic misses in the correction phase and allows for a robust approach to MBOPC.

Citation Download Citation

Ioana Graur, Scott Mansfield, Moahmed Gheith, and Mohamed Al-Imam "Real-time VT5 model coverage calculations during OPC simulations", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211R (21 March 2007); https://doi.org/10.1117/12.712394

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