Pixelwise integrated circuits involving a pixel-level analog-to-digital converter (ADC) are studied for 320 × 240
microbolometer focal plane arrays (FPAs). It is necessary to use the pixelwise readout architecture for decreasing the
thermal noise. However, it is hard to locate a sufficiently large integration capacitor in a unit pixel of FPAs because of
the area limitation. To effectively overcome this problem, a two step integration method is proposed.
First, after integrating the current of the microbolometer for 32&mgr;s, upper 5bits of the 13bit digital signal are output
through a pixel-level ADC. Then, the current of the microbolometer is integrated during 1ms after the skimming current
correction using upper 5bits in a field-programmable gate array (FPGA), and then lower 8bits are obtained through a
pixel-level ADC. Finally, upper 5bits and lower 8bits are combined into the digital image signal after the gain and offset
correction in digital signal processor (DSP)
Each 2×2 pixel shares an readout circuit, including a current-mode background skimming circuit, an operational
amplifier(op-Amp), an integration capacitor and a single slope ADC. When the current of a microbolometer is
integrated, the integration capacitor is connected between a negative input and an output of the op-Amp. Therefore a
capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. When the
output of a microbolometer is converted to digital signal, the Op-Amp is used as a comparator of the single slope ADC.
This readout circuit is designed to achieve 35×35&mgr;m2 pixel size in 0.35&mgr;m 2-poly 3-metal CMOS technology.