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9 April 2007 Smart Altera firmware for DSP with FPGAs
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Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of engineering skills ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink-based design flow. This not only allows the over 1 million MatLab users to design with FPGAs but also to by-pass the hardware design engineer and leads therefore to shorter development time. We have evaluated the Altera/Simulink tool flow used for a University design environment and present design experience of a semester course at FAMU-FSU College of Engineering. We discuss the required background knowledge, key target smart firmware for FPGAs and possible advanced designs, e.g. FFT and multirate filter banks and wavelets designed by students with only basic logic experience.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Uwe Meyer-Baese, A. Vera, A. Meyer-Baese, M. Pattichis, and R. Perry "Smart Altera firmware for DSP with FPGAs", Proc. SPIE 6576, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks V, 65760T (9 April 2007);

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