ASIC for high-speed-gating and free running operation of SPADs

Alexis Rochas; Christophe Guillaume-Gentil; Jean-Daniel Gautier; Alexandre Pauchard; Gregoire Ribordy; Hugo Zbinden; Yusuf Leblebici; Laurent Monat

doi:10.1117/12.722828

11 May 2007 ASIC for high-speed-gating and free running operation of SPADs

Alexis Rochas, Christophe Guillaume-Gentil, Jean-Daniel Gautier, Alexandre Pauchard, Gregoire Ribordy, Hugo Zbinden, Yusuf Leblebici, Laurent Monat

Author Affiliations +

Proceedings Volume 6583, Photon Counting Applications, Quantum Optics, and Quantum Cryptography; 65830F (2007) https://doi.org/10.1117/12.722828
Event: International Congress on Optics and Optoelectronics, 2007, Prague, Czech Republic

Abstract

Single photon detection at telecom wavelengths is of importance in many industrial applications ranging from quantum cryptography, quantum optics, optical time domain reflectometry, non-invasive testing of VLSI circuits, eye-safe LIDAR to laser ranging. In practical applications, the combination of an InGaAs/InP APD with an appropriate electronic circuit still stands as the best solution in comparison with emerging technologies such as superconducting single photon detectors, MCP-PMTs for the near IR or up-conversion technique. An ASIC dedicated to the operation of InGaAs/InP APDs in both gated mode and free-running mode is presented. The 1.6mm² chip is fabricated in a CMOS technology. It combines a gate generator, a voltage limiter, a fast comparator, a precise timing circuit for the gate signal processing and an output stage. A pulse amplitude of up to +7V can be achieved, which allows the operation of commercially available APDs at a single photon detection probability larger than 25% at 1.55&mgr;m. The avalanche quenching process is extremely fast, thus reducing the afterpulsing effects. The packaging of the diode in close proximity with the quenching circuit enables high speed gating at frequencies larger than 10MHz. The reduced connection lengths combined with impedance adaptation technique provide excellent gate quality, free of oscillations or bumps. The excess bias voltage is thus constant over the gate width leading to a stable single photon detection probability and timing resolution. The CMOS integration guarantees long-term stability, reliability and compactness.

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Alexis Rochas, Christophe Guillaume-Gentil, Jean-Daniel Gautier, Alexandre Pauchard, Gregoire Ribordy, Hugo Zbinden, Yusuf Leblebici, and Laurent Monat "ASIC for high-speed-gating and free running operation of SPADs", Proc. SPIE 6583, Photon Counting Applications, Quantum Optics, and Quantum Cryptography, 65830F (11 May 2007); https://doi.org/10.1117/12.722828

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