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10 May 2007 Automatic logic synthesis for parallel alternating latches clocking schemes
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Abstract
This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves the applicability of PALACS and its benefits. This technique is verified through design examples in three different CMOS processes and using logic level simulation, with successful results in all the cases.
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D. Guerrero, M. Bellido, J. Juan, A. Millan, P. Ruiz, E. Ostua, and J. Viejo "Automatic logic synthesis for parallel alternating latches clocking schemes", Proc. SPIE 6590, VLSI Circuits and Systems III, 659006 (10 May 2007); https://doi.org/10.1117/12.723664
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