HEAPAN: a high-level computer architecture analysis tool

Dionisio D. Peñalosa; Carlos J. Jiménez; Manolo Valencia

doi:10.1117/12.721972

23 May 2007 HEAPAN: a high-level computer architecture analysis tool

Dionisio D. Peñalosa, Carlos J. Jiménez, Manolo Valencia

Proceedings Volume 6590, VLSI Circuits and Systems III; 659008 (2007) https://doi.org/10.1117/12.721972
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain

Abstract

The non-stop advance of computer architectures and their wide variety, not only in types (pipeline, super pipeline, etc.) but also in application fields, as well as their high cost from conception to the implementation, make it necessary to have tools that, on the one hand, help to design and to evaluate processors comfortably, and, on the other, link up with commercial design flows of microelectronics circuits (in FPGA technologies or VLSI Deep-submicron). This work presents HEAPAN, a tool for the high level design and evaluation of processors. The main idea of this tool is to be able to describe a processor at high level easily and cheaply in order to compare different architectural options. Behavioural verifications are done at RT level, with descriptions automatically generated by HEAPAN. For the development of HEAPAN, a study of the most important distinctive features of major recent commercial processors has been carried out, and the most relevant blocks that make up these architectures have been extracted. These blocks have been implemented as functional units of the tool. In this way the construction of a processor with HEAPAN basically consists of selecting and interconnecting those blocks. Finally the validity of the developed tool has been tested through the design of a simple processor, verifying its behaviour and implementing it in a deep-submicron technology.

Citation Download Citation

Dionisio D. Peñalosa, Carlos J. Jiménez, and Manolo Valencia "HEAPAN: a high-level computer architecture analysis tool", Proc. SPIE 6590, VLSI Circuits and Systems III, 659008 (23 May 2007); https://doi.org/10.1117/12.721972

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available