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10 May 2007 Automatic synthesis of zero-aliasing space compactors with application to testing of embedded IP cores
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This paper presents a set of software tools for the synthesis of structure-independent single-output space compactors with application to combinational or scan-based digital circuits. The synthesized compactor compresses test responses of a circuit under test (CUT) to a periodic single-output data stream with guaranteed zero-aliasing. The compactor is designed using the knowledge of the expected fault-free responses of the circuit, being particularly suitable for intellectual property (IP) cores whose internal structure is frequently unknown. The space-compactor compares the actual response of the circuit in all of its functional outputs with the expected hardware-generated responses. When the circuit is fault-free, the successive responses provoke an alternate sequence of high and low levels in the single-output of the compactor. This periodicity of the response is broken in presence of a fault. Using this compactor, only one output is required to check the response of the combinational logic of the circuit. Moreover, the characteristics of the output make the storing test responses unnecessary, thus reducing the amount of test data. The sole input required by the set of tools developed is the set of test patterns generated for the circuit and the fault-free expected responses. When the internal structure of the circuit is known, only the patterns must be provided. The tools generate as output a high-level synthesizable description in VHDL of the complete space compactor. External tools as the well-known espresso or sis have been used to minimize the amount of logic or the number of logic levels of the compactor.
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José M. Solana and Javier Frechoso "Automatic synthesis of zero-aliasing space compactors with application to testing of embedded IP cores", Proc. SPIE 6590, VLSI Circuits and Systems III, 65900R (10 May 2007);

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