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23 May 2007 Toward systematic design of multi-standard converters
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Proceedings Volume 6590, VLSI Circuits and Systems III; 65900T (2007)
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital-Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard &Sgr;&Dgr; modulator meeting the specifications of three wireless communication standards.
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V. J. Rivas, R. Castro-López, A. Morgado, O. Guerra, E. Roca, R. del Río, J. M. de la Rosa, and F. V. Fernández "Toward systematic design of multi-standard converters", Proc. SPIE 6590, VLSI Circuits and Systems III, 65900T (23 May 2007);

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