23 May 2007 A methodology for switching noise estimation at gate level
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This paper provides a simple methodology, based on available CAD tools, able of extracting valuable information on supply current curves, otherwise limited by the layout disposal, making it impracticable for the present high density circuits. The approach starts at HDL level, which will be automatically synthesized to a gate level being the peak power (one peak per clock cycle) measured at this level, giving an idea of the switching noise generated. Although an indirect method, it provides a quantitative value of noise valid for comparison between different proposals. To assess the methodology two different tools are used: PrimePower and NanoSim, both from Synopsys, that generate an average power and a peak power value. We will see that NanoSim is good for noise estimation but this is not the case of PrimePower.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Javier Castro, Javier Castro, Pilar Parra, Pilar Parra, Antonio J. Acosta, Antonio J. Acosta, } "A methodology for switching noise estimation at gate level", Proc. SPIE 6590, VLSI Circuits and Systems III, 65900U (23 May 2007); doi: 10.1117/12.724164; https://doi.org/10.1117/12.724164


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