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10 May 2007 Low-cost VLSI architecture design for forward quantization of H.264/AVC
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Proceedings Volume 6590, VLSI Circuits and Systems III; 65900Y (2007) https://doi.org/10.1117/12.721493
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain
Abstract
The H.264/AVC (Advanced Video Codec) is the latest standard for video coding. It assumes a scalar forward quantizer performed at the encoder which can be implemented directly in integer arithmetic. An efficient architecture for the computation of forward quantization of H.264/AVC is presented in this paper. It uses a modification of the quantization operation which reduces the arithmetic operations, and a truncated Booth multiplier based on adaptative statistical approach, which reduces the hardware. The JM reference software's C code has been re-written to analyze the effect of new algorithm and of truncated Booth multiplier. Simulations made up over popular test sequences used in video standardization show the validity of this approach. These results demonstrate that, at low QP, the PSNR is improved between a maximum of +0.81db and a minimum of 0.31db, with a slight increase in the Bit Rate being around 0.8%. Finally, a suitable architecture for VLSI implementation is presented, which reduces in a 26% the area, 32% the power and 21% the critical path delay in comparison with classical implementation. Moreover, it also reduces the area and increase the speed in comparison with architectures presented in references.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
G. A. Ruiz and J. A. Michell "Low-cost VLSI architecture design for forward quantization of H.264/AVC", Proc. SPIE 6590, VLSI Circuits and Systems III, 65900Y (10 May 2007); https://doi.org/10.1117/12.721493
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