10 May 2007 High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC
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Abstract
This paper presents efficient integer-pel and fractional-pel motion estimation VLSI architectures for luma video component in H.264/AVC. The proposed architectures were designed as hardware accelerators for 32-bit processors to reduce computation cost and processing time. Both accelerators use the full-search block-matching algorithm to fulfil the standard requirements with maximum quality. The integer motion estimator is composed by a systolic 16x16 processing elements array with optimal memory management and effective data-path. The array was designed to adjust the search window size and shape at macroblock level without a high control overhead. Simulation results show computing and time reduction from 21.5%, to 60.7% using a search window shape different than square with a maximum PSNR degradation of 0.014 dB. The fractional motion estimation architecture improves time operation of previous designs by means of two parallel-pipeline stages, an effective block flow and faster interpolation modules. The design can process the 41 macroblock partitions and sub-partitions in quarter-pel resolution in 606 clock cycles. Operating at 100-MHz clock frequency, the architecture supports 720p HD video format @ 30 fps for one reference frame. Implementation results based on FPGA devices using VHDL are included.
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Armando Mora-Campos, Armando Mora-Campos, Francisco J. Ballester-Merelo, Francisco J. Ballester-Merelo, Marcos A. Martínez-Peiró, Marcos A. Martínez-Peiró, José A. Canals-Esteve, José A. Canals-Esteve, } "High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC", Proc. SPIE 6590, VLSI Circuits and Systems III, 659010 (10 May 2007); doi: 10.1117/12.724042; https://doi.org/10.1117/12.724042
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