23 May 2007 A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators
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This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade ΣΔ modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT ΣΔ modulator in a 1.2V 130nm CMOS technology.
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R. Tortosa, R. Tortosa, R. Castro-López, R. Castro-López, J. M. de la Rosa, J. M. de la Rosa, A. Rodríguez-Vázquez, A. Rodríguez-Vázquez, F. V. Fernández, F. V. Fernández, } "A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators", Proc. SPIE 6590, VLSI Circuits and Systems III, 659016 (23 May 2007); doi: 10.1117/12.721896; https://doi.org/10.1117/12.721896

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