10 May 2007 Dynamic power management of a system on chip based on AMBA AHB bus
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Abstract
This paper presents new dynamic voltage scaling and power management architectures for a System on Chip with an AMBA AHB bus. The Power State Machine describing the status of the core follows the recommendations of the ACPI standard. The algorithm controls the power states of each block on the basis of battery status, chip temperature and workload conditions. The DVS and DPM architectures proposed has been described at system level in SystemC. In particular, we investigated the possibility to change clock frequency and supply voltage for each master, slave and bus independently when no transfer is required. A system level analysis has been performed to evaluate the effect of different DVS and DPM algorithms, topologies and architectures on power dissipation and system performances.
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Simone Marinelli, Simone Marinelli, Massimo Conti, Massimo Conti, } "Dynamic power management of a system on chip based on AMBA AHB bus", Proc. SPIE 6590, VLSI Circuits and Systems III, 65901K (10 May 2007); doi: 10.1117/12.721892; https://doi.org/10.1117/12.721892
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