10 May 2007 New FPSoC-based architecture for efficient FSBM motion estimation processing in video standards
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Due to the timing constraints in real time video encoding, hardware accelerator cores are used for video compression. System on Chip (SoC) designing tools offer a complex microprocessor system designing methodologies with an easy Intellectual Property (IP) core integration. This paper presents a PowerPC-based SoC with a motion-estimation accelerator core attached to the system bus. Motion-estimation (ME) algorithms are the most critical part in video compression due to the huge amount of data transfers and processing time. The main goal of our proposed architecture is to minimize the amount of memory accesses, thus exploiting the bandwidth of a direct memory connection. This architecture has been developed using Xilinx XPS, a SoC platforms design tool. The results show that our system is able to process the integer pixel full search block matching (FSBM) motion-estimation process and interframe mode decision of a QCIF frame (176*144 pixels), using a 48*48 pixel searching window, with an embedded PPC in a Xilinx Virtex-4 FPGA running at 100 MHz, in 1.5 ms, 4.5 % of the total processing time at 30 fps.
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J. A. Canals, J. A. Canals, M. A. Martínez, M. A. Martínez, F. J. Ballester, F. J. Ballester, A. Mora, A. Mora, "New FPSoC-based architecture for efficient FSBM motion estimation processing in video standards", Proc. SPIE 6590, VLSI Circuits and Systems III, 65901N (10 May 2007); doi: 10.1117/12.724094; https://doi.org/10.1117/12.724094

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