10 May 2007 Temperature impact on multiple-input CMOS gates delay
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CMOS IC scaling has surpassed the 100nm barrier being now in the 65nm node with a rapid migration to the 35nm generation. In achieving the primary goals of technology scaling such as performance and density increase at a reduced cost per transistor, new side effects must be solved representing further challenges to the advance of the predicted roadmap. One of these challenges is related to the management of thermal-related effects such as hot-spots and overall junction temperature increase as they may have a significant impact on performance, power containment, circuit reliability, and even functionality. The adoption of adequate thermal management solutions requires a detailed analysis of the fundamental relationships governing the device and interconnect subsystem. Although much attention has been given to such analysis at the device and the logic inverter levels, less is known about such dependences in complex gates with transistor stacks. In this work we study the fundamental mechanisms underlying the temperature dependence of transistor stacks showing the key role of the stack dynamic threshold on the overall delay-temperature behavior at the gate level.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
C. de Benito, C. de Benito, S. Bota, S. Bota, J. L. Rosselló, J. L. Rosselló, J. Segura, J. Segura, } "Temperature impact on multiple-input CMOS gates delay", Proc. SPIE 6590, VLSI Circuits and Systems III, 65901Q (10 May 2007); doi: 10.1117/12.722148; https://doi.org/10.1117/12.722148


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