22 May 2007 A low-noise low-power EEG acquisition node for scalable brain-machine interfaces
Author Affiliations +
Abstract
Electroencephalograph (EEG) recording systems offer a versatile, noninvasive window on the brain's spatio-temporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 &mgr;W supports EEG systems with hundreds of electrodes to operate from small batteries for many hours. Coupling between the bit-serial output and the highly sensitive analog input due to dense integration of analog and digital functions on the circuit board results in a deterministic noise component in the output, larger than the intrinsic sensor and circuit noise. With software correction of this noise contribution, the system achieves an input-referred noise of 0.277 &mgr;Vrms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. A chain of seven nodes using EEG dry electrodes created in micro-electrical-mechanical system (MEMS) technology is demonstrated in a real-world setting.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Thomas J. Sullivan, Stephen R. Deiss, Gert Cauwenberghs, Tzyy-Ping Jung, "A low-noise low-power EEG acquisition node for scalable brain-machine interfaces", Proc. SPIE 6592, Bioengineered and Bioinspired Systems III, 659203 (22 May 2007); doi: 10.1117/12.724019; https://doi.org/10.1117/12.724019
PROCEEDINGS
8 PAGES


SHARE
Back to Top