18 June 2007 In-chip overlay metrology for 45nm processes
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Abstract
The feasibility of measuring overlay using small (between 1x1&mgr;m and 3x3&mgr;m total size) targets has been demonstrated4. The symmetry of the image of isolated test features changes with overlay offset. The targets are small enough to be positioned within active areas of the device, and total measurement uncertainty (TMU) is sufficient to allow these targets to be used in characterizing overlay variations in the active device. In this paper we describe further development of this technique and its application to overlay control in 45nm processes. A simple image model has been used to predict how the target images change with overlay error, and to study the unwanted effects of process variation on the measurement. In order to ensure the accuracy of measurements made using the in-chip targets it is necessary to provide for dynamic calibration of the symmetry-to-overlay response. This calibration can be readily achieved by printing multiple targets close together, with each target having a programmed offset that differs by a small amount. In our tests we have used triplets of targets with programmed offsets of 30nm, 50nm and 70nm. Normal targets are printed with a programmed offset of 50nm. A test reticle was designed for double-pass printing of a range of in-chip targets with different sizes and component dimensions, and with designed overlay offsets of 0nm to 100nm in 4nm steps. Standard bar-in-bar targets were printed with every in-chip target to allow the change of symmetry with overlay to be measured directly. Wafers were printed using a 45nm process poly-to-STI stack. Measurements were made in multiple fields and from multiple wafers using an unmodified Nanometrics Caliper élan overlay tool. The test wafers were printed with extremes of process variation. Correlation of the measured image symmetry to the programmed offset under different process conditions shows that the response is sensitive to film changes, as predicted by the image model. Results from production wafers show that the effect of normal process variation is small enough that calibration is not necessary at every location. Placing a few calibration targets in the scribe lines of the device is more than sufficient, allowing the smallest possible space requirement for measurement inside the active area of the device. Detailed study of the change in overlay with programmed offset along a line of test samples with the same design properties shows short-scale variations of order 1-5nm. According to the 2005 ITRS1 these variations account for nearly 50% of the overlay budget for a 45nm process. This effect cannot be described by any model where overlay variations are purely a mathematical function of position, and in process control at this node it will become necessary to use characterization of overlay by measurement instead of models.
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Y. S. Ku, Y. S. Ku, H. L. Pang, H. L. Pang, N. P. Smith, N. P. Smith, L. Binns, L. Binns, } "In-chip overlay metrology for 45nm processes", Proc. SPIE 6617, Modeling Aspects in Optical Metrology, 66170X (18 June 2007); doi: 10.1117/12.726051; https://doi.org/10.1117/12.726051
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