31 May 2007 Fault tolerant techniques for integrated circuits in submicron and nanotechnologies
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Proceedings Volume 6635, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies III; 66350B (2007); doi: 10.1117/12.741873
Event: Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies III, 2006, Bucharest, Romania
Abstract
Drastic device shrinking, power supply reduction, and increasing operating speeds that accompany the technological evolution to deeper submicron, reduce significantly the noise margins and thus the reliability of deep submicron ICs. A more significant problem is related to the single-event upsets (SEUs). It is predicted that neutrons produced by the sun activity will affect dramatically the operation of future Integrated Circuits (Ics). Self-test and fault tolerance in submicron and nanotechnologies becoming hitherto imperative. Perhaps the most significant problem concerns the sensitivity of future IC generations face to various noise sources, and in particularly face to energetic particles. This paper analyses some of designing soft-error tolerant circuits.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Angelica Bacivarov, "Fault tolerant techniques for integrated circuits in submicron and nanotechnologies", Proc. SPIE 6635, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies III, 66350B (31 May 2007); doi: 10.1117/12.741873; https://doi.org/10.1117/12.741873
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Logic

Clocks

Computer aided design

Nanotechnology

Integrated circuits

Tolerancing

Multiplexing

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