Defect reduction progress in step and flash imprint lithography

K. Selenidis; J. Maltabes; I. McMackin; J. Perez; W. Martin; D. J. Resnick; S. V. Sreenivasan

doi:10.1117/12.747565

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16 November 2007 Defect reduction progress in step and flash imprint lithography

K. Selenidis, J. Maltabes, I. McMackin, J. Perez, W. Martin, D. J. Resnick, S. V. Sreenivasan

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Proceedings Volume 6730, Photomask Technology 2007; 67300F (2007) https://doi.org/10.1117/12.747565
Event: SPIE Photomask Technology, 2007, Monterey, California, United States

Abstract

Imprint lithography has been shown to be an effective method for the replication of nanometer-scale structures from a template mold. Step and Flash Imprint Lithography (S-FIL^®) is unique in its ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer. The novelty of this process immediately raises questions about the overall defectivity level of S-FIL. Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This report specifically focuses on this challenge and presents the current status of defect reduction in S-FIL technology and will summarize the result of defect inspections of wafers patterned using S-FIL. Wafer inspections were performed with a KLA Tencor- 2132 (KT-2132) automated patterned wafer inspection tool. Recent results show wafer defectivity to be less 5 cm^-2. Mask fabrication and inspection techniques used to obtain low defect template will be described. The templates used to imprint wafers for this study were designed specifically to facilitate automated defect inspection and were made by employing CMOS industry standard materials and exposure tools. A KT-576 tool was used for template defect inspection.

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K. Selenidis, J. Maltabes, I. McMackin, J. Perez, W. Martin, D. J. Resnick, and S. V. Sreenivasan "Defect reduction progress in step and flash imprint lithography", Proc. SPIE 6730, Photomask Technology 2007, 67300F (16 November 2007); https://doi.org/10.1117/12.747565

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