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16 November 2007 Use of layout automation and design-based metrology for defect test mask design and verification
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This paper studies the impact of shape and local environment (pattern layout) on the ability to detect defects on the reticle and the extent to which they affect the dimension of the printed image on the wafer. The authors have made extensive use of design information to perform a thorough evaluation. OPC software was used to generate mask data that was comparable to product mask data. Defects were placed on the post-OPC layout and OPC software was also used to simulate the dimension of the defective features as printed on the wafer. "Design Based Metrology" was used to create accurate metrology recipes to support wafer and mask metrology. Ultimately the procedures described in this paper allow a direct correlation to be made between reticle inspectability and the impact of the same defects on wafer CD. Data is presented for the case of the Contact Hole layer of a "65nm" Logic technology, though the methods described in the paper are applicable to all layers.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chris Spence, Cyrus Tabery, Andre Poock, Arndt C. Duerr, Thomas Witte, Jan Fiebig, and Jan Heumann "Use of layout automation and design-based metrology for defect test mask design and verification", Proc. SPIE 6730, Photomask Technology 2007, 67300P (16 November 2007);


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