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30 October 2007 Selecting and using a lithography compliance DFM tool for 65-nm foundry production
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DFM tools have been all the rage in recent years. By exposing potential manufacturability, timing and variation issues early, these tools can help the designers correct such issues before the tape out. Such an early intervention delivers a faster yield ramp for the product. For the lower volume devices, the faster yield ramp can help meet the market window while for higher volume devices it can also mean millions of dollars in cost savings. While there have been several DFM product announcements, case studies focusing on actual usage of such tools are not publicly available. In this article we share the data from a real customer evaluation and deployment. This North American customer has deployed the tool and completed several TSMC 65nm layouts. By focusing on the motivation to use such a tool, the article will first quantify the expected value from such a tool. Next the article will present the detailed evaluation criteria for choosing a tool. Finally, actual error data from production tape outs and performance metrics of the LCC tool will be presented showing runtime, scalability and memory numbers.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Babak Hatamian and Rahul Kapoor "Selecting and using a lithography compliance DFM tool for 65-nm foundry production", Proc. SPIE 6730, Photomask Technology 2007, 673011 (30 October 2007);

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