2 May 2008 Controlling linewidth roughness in step and flash imprint lithography
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Proceedings Volume 6792, 24th European Mask and Lithography Conference; 67920W (2008) https://doi.org/10.1117/12.798936
Event: 24th European Mask and Lithography Conference, 2008, Dresden, Germany
Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gerard M. Schmid, Gerard M. Schmid, Niyaz Khusnatdinov, Niyaz Khusnatdinov, Cynthia B. Brooks, Cynthia B. Brooks, Dwayne LaBrake, Dwayne LaBrake, Ecron Thompson, Ecron Thompson, Douglas J. Resnick, Douglas J. Resnick, Jordan Owens, Jordan Owens, Arnie Ford, Arnie Ford, Shiho Sasaki, Shiho Sasaki, Nobuhito Toyama, Nobuhito Toyama, Masaaki Kurihara, Masaaki Kurihara, Naoya Hayashi, Naoya Hayashi, Hideo Kobayashi, Hideo Kobayashi, Takashi Sato, Takashi Sato, Osamu Nagarekawa, Osamu Nagarekawa, Mark W. Hart, Mark W. Hart, Kailash Gopalakrishnan, Kailash Gopalakrishnan, Rohit Shenoy, Rohit Shenoy, Ron Jih, Ron Jih, Ying Zhang, Ying Zhang, Edmund Sikorski, Edmund Sikorski, Mary Beth Rothwell, Mary Beth Rothwell, Shusuke Yoshitake, Shusuke Yoshitake, Hitoshi Sunaoshi, Hitoshi Sunaoshi, Kenichi Yasui, Kenichi Yasui, } "Controlling linewidth roughness in step and flash imprint lithography", Proc. SPIE 6792, 24th European Mask and Lithography Conference, 67920W (2 May 2008); doi: 10.1117/12.798936; https://doi.org/10.1117/12.798936

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